1. Field of the Invention
This invention relates to improvements in mass data storage devices, or the like, and more particularly to improvements in polyphase dc motor driver circuits for use in mass data storage devices, or the like, and still more particularly to improvements in circuits used to control the commutation current slew rate in polyphase dc motor driver circuits for use in mass data storage devices, or the like.
2. Relevant Background
A conventional low-side current-mode power amplifier circuit 10 used in the prior art is shown in FIG. 1. The circuit may be used as a low-side driver circuit in a commutated motor drive circuit with an accompanying high-side driver circuit (not shown). The power amplifier 10 is connected to drive to a low potential one phase of a DC motor (not shown), which may include multiple phases, typically three phases, to which current is commutatively switched in known manner.
More particularly, the circuit 10 is connected to one of the coils 12 of the motor to sink current in the phase through a NMOS transistor 14. The NMOS transistor 14 is referred to herein as a power FET. A resistance 16 is associated with the coil 12 of value R.sub.M. The inductance of the coil 12 is L.sub.M.
As shown in FIG. 1, a linear reference current input is converted into a voltage across resistor 26. The voltage is then provided to the non-inverting node of an OTA 22 whose output drives the gate of the power FET 14 as well as a mirror FET 20. An identical or ratioed magnitude of the current in the mirror FET 20 is thus mirrored by the diode-connected FET 32 in its mirror FET 30 and then converted into a voltage across resistor 24 and fed back to the inverting node of the OTA 22. The high gain of the OTA 22 forces the currents flowing through resistors 24 and 26 to be substantially equal provided that resistors 24 and 26 are equal. The dominant pole of this circuit is set by the gate capacitance of the power FET 14.
The current through the mirror FET 20 is controlled by the OTA 22 which has an inverting input connected to a resistor 24 through which a current flows and a non-inverting input connected to a resistor 26 through which a reference current supplied by a constant current source 28 flows. The diode-connected FET 32 with its mirror FET 30 controls the current through resistor 24. It should be noted that the current I.sub.MOTOR through the power FET 14 is proportional to the current through the mirror FET 20. Thus, controlling the current though the mirror FET 20 provides a means to control the current through the power FET 14.
However, the current flowing through the mirror FET 20 is not linearly proportional to the current flowing through the power FET 14, due to possibly substantial difference in their drain-to-source voltages in both transient and steady-stage responses. Most of all, the design of the OTA can be rather difficult due to the low-frequency pole introduced by the inherent motor inductance L.sub.M and the motor resistance R.sub.M. In most cases, the loop bandwidth must be severely compromised to guarantee the loop stability.